1. Technical Field
The present invention relates to a network processor, and more particularly to a method for processing various numbers of ports in a network processor.
2. Related Art
In recent times, Internet subscribers (called “netizens”) have increased rapidly, and further, a new Internet service such as integration between voice and data and integration between the wired/wireless Internets, etc. has become increasingly popular as a substitute for a typical Internet service. To accomplish this new Internet service, a typical network system must be newly upgraded to have more intelligence and be operated at a super-high speed. To support such a system, a packet-processing fundamental component having a wide bandwidth is indispensable. However, since a typical ASIC (Application Specific Integrated Circuit)-based network equipment used for an Internet uses a silicon chip, it is impossible to add a new function or enhance its existing performance, and its packet-processing capacity is limited within a predetermined range. Therefore, network equipment based on the next generation silicon chip may be being developed.
Generally, a network processor (NP) is a kind of a programmable processor that is capable of processing a packet in various methods before transmitting the packet received at an input user interface (i.e., an input port) to an output user interface (i.e., an output port), and is a specific packet processor having advantages in that it provides a high-performance packet-processing capacity and immediately reflects various desires of network users by means of a program.
The network processor is a non-memory semiconductor serving as fundamental components for the next generation network equipment. The non-memory semiconductor performs a traffic transmission between ports in network equipment such as a router and switch, and performs a programming for an intelligent switching function in such a way that various kinds of multimedia Internet traffic services are available. Therefore, many manufacturers of communication chips have developed such a network processor in light of “cost-effective” and “time-to-market” products. For example, representative manufacturers, such as an Intel, IBM, Vitesse, and AMCC Corporations, etc., have competed with one another to develop a new network processor and an enhanced version.
In the meantime, many companies developing network equipment using the aforementioned network processor have considered a type of user interfaces, the number of user interfaces, and a speed of user interfaces as the most important matters. For example, there are various kinds of user interfaces, that is, T1, E1, Fast Ethernet, Gigabit Ethernet, OC-3, OC-12, and OC-48, etc. A program in a typical network processor has a fixed program structure in that a fixed number of ports are supported by a given user interface type or a hardware designer. For example, in case of a system supporting Fast Ethernet user interface 16-ports, a system designer develops a fixed-structure program for processing input packets received from the 16 ports.
In this case, a program designer is capable of maximizing a program performance after fixing a program structure. However, in case of changing the number of ports, the program designer must develop other programs due to a problem of a network processor. That is, in the case where a network processor has a wrong structure or a wrong program while making its own internal program, it does not reuse a program or degrades a program extension even though it is a programmable processor.
For example, an “IXP1200” manufactured by the Intel Corporation is a network processor for a packet processing, and has a “Layer 2 switching” function and a “Layer 3 routing” function. In the future, the IXP1200 will provide various kinds of functions, e.g., a traffic engineering, QoS (Quality of Service), MPLS (Multi-Protocol Label Switching), and ATM (Asynchronous Transfer Mode), etc., that are useful to a communication circuitry field. However, for a microcode structure (e.g., an Intel network processor program) of the IXP1200, it is difficult to extend the number of ports, because it processes a fixed number of ports in consideration of a processing performance of the IXP1200 or allocates a predetermined port to a microengine (e.g., an IXP1200's packet processing engine).
Exemplars of recent efforts in the art of networking are disclosed, for example, in U.S. Pat. No. 6,078,964 to Ratcliff et al. entitled ESTABLISHING DIRECT COMMUNICATIONS BETWEEN TWO HOSTS WITHOUT USING A HIGH PERFORMANCE LAN CONNECTION, issued on Jun. 20, 2000, and U.S. Pat. No. 5,809,527 to Cooper et al., entitled OUTBOARD FILE CACHE SYSTEM, issued on Sep. 15, 1998.
While these contemporary efforts contain merit, it is our observation that further improvements can also be contemplated.
In conclusion, in the case where extending the number of ports is needed depending on the type of user interfaces or the designer's intention, the microcode structure must be changed so that the whole code must be changed too. Also, in case of various user interfaces, the designer must develop many microcode sets to satisfy all the user interfaces.